Dynamic branch hints using branches-to-nowhere conditional branch
AssigneeIntel Corporation
InventorsAndrew T. Forsyth, Renju Thomas, Jean-Luc Duprat
Life of this patent
Estimating the term…
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AssigneeIntel Corporation
InventorsAndrew T. Forsyth, Renju Thomas, Jean-Luc Duprat
Estimating the term…
A processor includes an execution pipeline having one or more execution units to execution the instructions and a branch prediction unit coupled to the execution units. The branch prediction unit includes a branch history table to store prior branch predictions, a branch predictor, in response to a conditional branch instruction, to predict a branch target address of the conditional branch instruction based on the branch history table, and address match logic to compare the predicted branch target address with an address of a next instruction executed immediately following the conditional branch instruction. The address match logic is to cause the execution pipeline to be flushed if the predicted branch target address does not match the address of the next instruction to be executed.
A processor, comprising:
A computer implemented method, comprising:
A data processing system, comprising:
Dependencies are inferred from the claim text.