Branch prediction with power usage prediction and control
AssigneeInternational Business Machines Corporation
InventorsMark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
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Abstract
A method and circuit arrangement maintain power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
Claims25
A circuit arrangement, comprising:
- a processing unit including a fixed point execution and a floating point execution unit;
- branch prediction logic disposed in the processing unit, the branch prediction logic including a branch history table including a plurality of entries, wherein each entry in the branch history table is associated with a branch instruction and includes at least one branch history bit predicting whether the associated branch instruction will be taken, and wherein each entry in the branch history table further includes at least one power usage prediction bit predicting whether the floating point execution unit is expected to be idle subsequent to execution of the associated branch instruction;
- tracking logic coupled to the branch prediction logic and configured to notify the branch prediction logic of an idle status of the floating point execution unit, the tracking logic including:
- a counter configured to track a number of cycles the floating point execution unit has remained idle;
- and
- a latch configured to store an address associated with a last branch instruction;
- and
- control logic coupled to the branch prediction logic and configured to selectively reduce power consumption of the floating point execution unit in association with execution of a first branch instruction based upon the at least one power usage prediction bit in a first entry in the branch prediction table for the first branch instruction.
A circuit arrangement, comprising:
- a processing unit including a plurality of functional units;
- branch prediction logic coupled to the processing unit and configured to maintain historical information associated with a plurality of branch instructions, wherein the historical information for a first branch instruction among the plurality of branch instructions further includes power usage prediction information associated with a first functional unit among the plurality of functional units;
- and
- control logic coupled to the branch prediction logic and configured to selectively reduce power consumption of the first functional unit in association with execution of the first branch instruction based upon the power usage prediction information maintained by the branch prediction logic.
A method of controlling power consumption in a processing unit of the type including a plurality of functional units, the method comprising:
- maintaining, in branch prediction logic coupled to the processing unit, historical information associated with a plurality of branch instructions, wherein the historical information for a first branch instruction among the plurality of branch instructions further includes power usage prediction information associated with a first functional unit among the plurality of functional units;
- and
- selectively reducing power consumption of the first functional unit in association with execution of the first branch instruction based upon the power usage prediction information maintained by the branch prediction logic.
Dependencies are inferred from the claim text.