Loading patent…
OwnerLaura A. Knauth, Peggy J. Irelaninventors
Estimating the term…
A processor includes a core that includes an execution engine unit for executing instructions, a controller, and a storage having stored thereon a statistical sampling record, in which in response to occurrence of a hardware event caused by executing an instruction, the controller is configured to: (1) determine an instruction pointer (IP) pointed to the instruction that actually caused the hardware event; and (2) write the IP as an Eventing IP in a field of the statistical sampling record. The controller is further configured to determine a data address at which a load/store operation associated with the instruction accesses data, and write the data address to a data address field of the statistical sampling record.
A processor, comprising:
A controller embedded in a core of a processor that includes an execution engine unit for executing instructions, the controller being configured to access a storage having stored thereon a statistical sampling record that includes a field for, in response to occurrence of a hardware event caused by executing an instruction, storing, as an Eventing IP, an instruction pointer (IP) pointed to the instruction that actually caused the hardware event.
A method for managing a statistical sampling record of a processor, comprising:
A system comprising:
Dependencies are inferred from the claim text.