US 2014/0229713 A1 · EXTENSIBLE EXECUTION UNIT INTERFACE ARCHITECTURE

Abstract

A method and circuit arrangement tightly couple together decode logic associated with multiple types of execution units and having varying priorities to enable instructions that are decoded as valid instructions for multiple types of execution units to be forwarded to a highest priority type of execution unit among the multiple types of execution units. Among other benefits, when an auxiliary execution unit is coupled to a general purpose processing core with the decode logic for the auxiliary execution unit tightly coupled with the decode logic for the general purpose processing core, the auxiliary execution unit may be used to effectively overlay new functionality for an existing instruction that is normally executed by the general purpose processing core, e.g., to patch a design flaw in the general purpose processing core or to provide improved performance for specialized applications.

Claims16

Dependent claims

A circuit arrangement, comprising:

first decode logic associated with a first type of execution unit and configured to receive an instruction and decode the instruction;
and
second decode logic associated with a second type of execution unit and configured to receive the instruction and decode the instruction, wherein the instruction is concurrently forwarded to the first and second decode logic;
wherein the first decode logic has a higher priority than the second decode logic such that if the first and second decode logic respectively decode the instruction as a valid instruction for the first and second types of execution unit, the instruction is executed by a first execution unit of the first type of execution unit rather a second execution unit of the second type of execution unit.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

13/793,443Filed 11 Mar 2013

Priority

13 Feb 2013

Published

14 Aug 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3016
Instruction analysis, e.g. decoding, instruction word fields: decoding the operand specifier, e.g. specifier format
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/3822
Decoding for concurrent execution: parallel decoding, e.g. parallel decode units
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…

Extensible execution unit interface architecture

Life of this patent

Extensible execution unit interface architecture

Life of this patent

Abstract

Claims16