Electronics apparatus able to revise micro-program and algorithm to revise micro-program
AssigneeSumitomo Electric Industries, Ltd.
InventorRyutaro FUTAMI
Life of this patent
Estimating the term…
Abstract
An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with the master CPU via an auxiliary interface independent of the inner interface (bus), the micro-program to be revised and stored in the memory of the slave CPU is transferred to the memory of the master CPU through the auxiliary interface. Auxiliary interface is cut during the normal operation of the master CPU.
Claims11
An electronic apparatus, comprising:
- a master central processing unit (CPU) configured to couple with a host system through an outer interface, the master CPU including a first memory;
- a slave CPU configured to couple with the master CPU through an inner interface, the secondary CPU including a second memory to store a data sent from a host system to the master CPU through the outer interface and transferred to the slave CPU through the inner interface;
- and
- a circuit element configured to couple with the slave CPU through an upstream auxiliary interface and the master CPU with a downstream auxiliary interface, the circuit element temporarily connecting the upstream auxiliary interface with the downstream auxiliary interface when the data stored in the second memory is transferred to the first memory.
A method to rewrite a micro-program stored in a memory in a master central processing unit (CPU), comprising steps of:
- sending a revised micro-program from a host system to the master CPU;
- transferring the revised micro-program to a memory of a slave CPU;
- interrupting the master CPU to stop an execution of a micro-program store in the memory;
- connecting the slave CPU with the master CPU thorough a upstream auxiliary interface pulled out from the slave CPU, a switch connected to the upstream auxiliary interface, and a downstream auxiliary interface connecting the switch with the master CPU;
- rewriting the micro-program stored in the memory of the master CPU with the revised micro-program through the upstream auxiliary interface, the switch, and the downstream auxiliary interface;
- and
- restarting the master CPU.
Dependencies are inferred from the claim text.