Systems and Methods for Accommodating End of Transfer Request in a Data Storage Device

A system for data processing, the system comprising:

• an input buffer operable to maintain a first data set and a second data set;
• a data detector circuit operable to:
• apply a data detection algorithm to the first data set to yield a first detected output, and
• apply the data detection algorithm to the second data set to yield a second detected output;
• a data decoder circuit operable to:
• apply a data decode algorithm to a first decoder input derived from the first detected output to yield a first decoder output, and
• apply the data decode algorithm to a second decoder input derived from the second detected output to yield a second decoder output;
• a scheduling circuit operable to:
• determine a remaining portion (ELB) of an end of burst latency value;
• scheduling processing of the first data set by the data decoder circuit according to a first scheduling algorithm based at least in part on the ELB being less than a threshold;
• and
• scheduling processing of the first data set by the data decoder circuit according to a second scheduling algorithm when the ELB is greater than the threshold.

A data storage device, the storage device comprising:

• a storage medium, wherein the storage medium includes at least a representation of a first data set and a representation of a second data set;
• a head assembly disposed in relation to the storage medium and operable to provide a first sensed signal corresponding to the representation of the first data set and a second senses signal corresponding to the representation of the second data set;
• a read channel circuit including:
• an analog front end circuit operable to provide a first analog signal corresponding to the first sensed signal and a second analog signal corresponding to the second sensed signal;
• an analog to digital converter circuit operable to sample the first analog signal to yield a first series of digital samples and to sample the second analog signal to yield a second series of digital samples;
• an equalizer circuit operable to equalize the first series of digital samples to yield a first data set and to equalize the second series of digital samples to yield a second data set;
• an input buffer operable to maintain a first data set and a second data set;
• a data detector circuit operable to:
• apply a data detection algorithm to the first data set to yield a first detected output, and
• apply the data detection algorithm to the second data set to yield a second detected output;
• a data decoder circuit operable to:
• apply a data decode algorithm to a first decoder input derived from the first detected output to yield a first decoder output, and
• apply the data decode algorithm to a second decoder input derived from the second detected output to yield a second decoder output;
• a scheduling circuit operable to:
• determine a remaining portion (ELB) of an end of burst latency value;
• scheduling processing of the first data set by the data decoder circuit according to a first scheduling algorithm based at least in part on the ELB being less than a threshold;
• and
• scheduling processing of the first data set by the data decoder circuit according to a second scheduling algorithm when the ELB is greater than the threshold.