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US 2014/0229677 A1Published application
Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses
AssigneeIntel Corporation
InventorsIlhyun Kim, Alexandre J. Farcy, Choon Wei Khor, Robert L. Hinton
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Abstract
This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses. This allows overlapping the ITLB and IC miss stall cycles with older instruction byte reads or older IC misses, resulting in fewer stalls than previous implementations and improved performance
Claims21
A processor comprising:
- a branch prediction unit (BPU) having logic to create branch predictions and fetch addresses;
- an instruction fetch unit (IFU) tag, coupled with the BPU, having logic to:
- perform instruction translation look-aside buffer (ITLB) and instruction cache (IC) tag lookups and
- send a fetch request to a page miss handler (PMH) when an ITLB miss occurs, or to lower level memory when an IC miss and an instruction stream buffer (ISB) miss occurs;
- and
- IFU data, decoupled from the BPU and IFU tag, having logic to:
- retrieve instruction bytes from the IC or the ISB based on the tag lookups, and
- send the instruction bytes through decode logic to an execution pipeline.
5 more elements
An apparatus comprising:
- a first logic to create branch predictions and fetch addresses;
- a second logic, coupled with the first logic, to send an instruction translation buffer (ITLB) request to a page miss handler (PMH) when an ITLB miss occurs, and a fetch request to lower level memory when an instruction cache (IC) miss and an instruction stream buffer (ISB) miss occurs for the fetch addresses;
- and
- a third logic, decoupled from the first logic and the second logic, to retrieve instruction bytes from the IC or the ISB based on the tag lookups, the retrieved bytes sent to an execution pipeline.
1 more element
A computer-implemented method comprising:
- generating branch predictions and fetch addresses in a first pipeline;
- performing, in the first pipeline, instruction translation look-aside buffer (ITLB) and instruction cache (IC) tag lookups for the fetch addresses;
- sending, in the first pipeline, a fetch request to lower level memory when an IC miss and an instruction stream buffer (ISB) miss occur;
- and
- retrieving, using a second pipeline that is decoupled from the first pipeline, instruction bytes from the IC or the ISB based on the tag lookups, the instruction bytes from the ISB including instruction bytes retrieved in advance from the fetch request.
2 more elements
Dependencies are inferred from the claim text.