Memory controller and memory control method

A memory controller that is connected to a memory module which is compliant with a DDR3 memory interface, the memory controller comprising:

• DQS control unit that outputting a data strobe signal DQS to a memory element, the DQS control unit being provided for each of the memory elements included in the memory module;
• DQ control unit that signal DQS, outputting write data, and receiving read data in synchronization with the date strobe signal DQS, the DQ control unit being provided for each of the memory element included in the memory module, and the data strobe signal DQS being output to the memory element;
• and
• write leveling control unit that controlling write levelling, the write leveling being performed at the time of initialization, wherein
• the DQS control unit comprises a DQS delay unit that delaying an output timing of the data strobe signal DQS by a delay amount that is set by the write leveling control unit,
• the DQ control unit comprises a DQ delay unit that delaying an output timing of the write data and a reception timing of the read data by the delay amount that is set by the write leveling control unit,
• at the time of the write leveling, after adjustment of a delay amount of less than one clock cycle is performed on the DQS delay unit and the DQ delay unit, the write leveling control unit compares a read data sequence, which is obtained by reading the read data sequence after writing an expected value data sequence and, with the expected value data sequence for each of the memory elements and adjusts the delay amount by a unit of a clock cycle in accordance with a result of a comparison for each of the DQS delay unit and the DQ delay unit,
• at the time of the writing, the write leveling control unit controls the DQS control unit to output the data strobe signal DQS that is longer than a burst length, which is defined in a standard, by “2*M”(M:
• an integer of one or greater) clock cycle, and controls the DQ control unit to add M pieces of data to a beginning and an end of the expected value data sequence, in which the number of data included in the expected value data sequence matches the burst length, and to output the expected value data sequence with the added data.