Requests and data handling in a bus architecture
AssigneeImagination Technologies Limited
InventorJason Meredith
Life of this patent
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AssigneeImagination Technologies Limited
InventorJason Meredith
Estimating the term…
Aspects relate to methods and systems for processing requests and sending data in a bus architecture. At least one master device is connected to at least two slave devices via a bus. An allocator allocates incoming requests from the master device to a target slave device. Incoming requests are buffered for the respective slave device. The master device sends a read request for a first slave device to the bus; the allocator generates a current-state indicator associated with the read request. The allocator generates a priority indicator associated with the read request. If the initial value of the current-state indicator equals the value of the priority indicator, the read request is processed; or if the initial value of the current-state indicator does not equal the value of priority indicator, the read request is deferred until a later time.
A system on chip, comprising
A method for use in a system on chip, comprising:
Dependencies are inferred from the claim text.