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US 2014/0229641 A1Published application
Method and apparatus for latency reduction
AssigneeMarvell World Trade Ltd.
InventorsShawn CHEN, Wei Jiang, Lin Chen
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosure provide an integrated circuit that includes a plurality of input/output (IO) circuits, an instruction receiving circuit and control circuits. The IO circuits are configured to receive a plurality of bit streams corresponding to an instruction to the integrated circuit. The instruction receiving circuit is configured to form the instruction from the plurality of bit streams. The control circuits are configured to operate according to the instruction.
Claims18
An integrated circuit, comprising:
- a plurality of input/output (IO) circuits configured to receive a plurality of bit streams corresponding to an instruction to the integrated circuit;
- an instruction receiving circuit configured to form the instruction from the plurality of bit streams;
- and
- control circuits configured to operate according to the instruction.
1 more element
A method, comprising:
- receiving, by a plurality of input/output (IO) circuits of an integrated circuit, a plurality of bit streams corresponding to an instruction to the integrated circuit;
- forming, by an instruction receiving circuit, the instruction from the plurality of bit streams;
- and
- controlling control circuits in the integrated circuit to operate according to the instruction.
1 more element
An integrated circuit, comprising:
- a control circuit configured to generate a plurality of instruction bit streams corresponding to an instruction to another integrated circuit;
- and
- a plurality of input/output (IO) circuits configured to output the plurality of instruction bit streams in order to send the instruction to the other integrated circuit.
Dependencies are inferred from the claim text.