Self-aligned insulating etchstop layer on a metal contact

A method for forming a semiconductor device, comprising:

• providing a substrate having a transistor that includes a sacrificial gate electrode;
• forming a first interlayer dielectric (ILD) over the substrate and the sacrificial gate electrode, wherein a top surface of the first ILD is substantially coplanar with an exposed top surface of the sacrificial gate electrode;
• removing the sacrificial gate electrode to form a first via;
• disposing a metal gate electrode into the first via, wherein a top surface of the metal gate electrode is substantially coplanar with the top surface of the first ILD;
• exposing the top surfaces of the first ILD and the metal gate electrode to a silane that selectively functionalizes the top surface of the first ILD and not the top surface of the metal gate electrode, wherein the functionalized top surface of the first ILD inhibits growth of a non-conductive metal oxide layer;
• growing a non-conductive metal oxide layer on the metal gate electrode;
• forming a second ILD over the first ILD and the non-conductive metal oxide layer;
• etching through the first and second ILD layers with an etching process, wherein the non-conductive metal oxide layer is resistant to the etching process;
• and
• disposing a second metal in the contact via to form S/D contacts to the S/D region, wherein the non-conductive metal oxide layer prevents a short between the metal gate electrode and the S/D contacts.

A method for forming a semiconductor device, comprising:

• providing a substrate having a transistor that includes a sacrificial gate electrode and non-conductive spacer layers formed along sidewalls of the sacrificial gate electrode;
• forming a first interlayer dielectric (ILD) over the substrate, the sacrificial gate electrode and the non-conducting spacer layers;
• planarizing the first ILD, such that a top surface of the first ILD is substantially coplanar with exposed top surfaces of the sacrificial gate electrode and the non-conductive spacer layers;
• removing the sacrificial gate electrode to form a first via;
• disposing a gate dielectric material along a bottom surface and sidewalls of the first via to form a gate dielectric layer;
• disposing a metal gate electrode into the first via, wherein a top surface of the metal gate electrode is substantially coplanar with the top surface of the first ILD;
• exposing the top surfaces of the first ILD, the non-conductive spacer layers, the gate dielectric material, and the metal gate electrode to a silane that selectively functionalizes top surfaces of the first ILD, the non-conductive spacer layers, and the gate dielectric material, but not the metal gate electrode, wherein the functionalized top surfaces inhibit the growth of a non-conductive metal oxide layer;
• growing a non-conductive metal oxide layer on the metal gate electrode;
• removing the silane from the top surfaces of the first ILD, the non-conductive spacer layers, and the gate dielectric;
• forming a second ILD over the first ILD, the non-conductive spacer layers, the gate dielectric layer, and the non-conductive metal oxide layer;
• etching through the first and second ILD layers with an etching process, wherein the non-conductive spacer layer, the gate dielectric layer, and the non-conductive metal oxide layer are resistant to the etching process;
• and
• disposing a second metal in the contact via to form S/D contacts to the S/D region, wherein the non-conductive metal oxide layer prevents a short between the metal gate electrode and the S/D contacts.