Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using cmos wells

A method for forming an integrated circuit (IC), the method comprising:

• providing a semiconductor substrate;
• forming a first well by implanting dopants of one conductivity type in the semiconductor substrate in a plurality of successively deeper first implantations with a deepest one of the first implantations having a first range defining a first well depth at which a maximum implanted dopant concentration occurs, the first well depth being greater than or equal to an isolation depth of shallow trench isolation structures formed in the semiconductor substrate, the plurality of successively deeper first implantations being used to concurrently form wells of the one conductivity type in a dual well CMOS process;
• forming at least one second well by implanting dopants of another conductivity type in a plurality of successively deeper second implantations with a deepest one of the second implantations having a second range defining a second well depth at which a maximum implanted dopant concentration occurs, the second well depth being greater than or equal to the isolation depth spaced from the first well in the semiconductor substrate by a lateral spacing distance and facing at least one lateral side of the body region of the first well, leaving a well-free portion of the semiconductor substrate extending laterally between the first and second wells, the plurality of successively deeper second implantations being used to concurrently form wells of the other conductivity type in the dual well CMOS process;
• forming first and second contact structures individually connected to spaced first and second regions of the first well.