US 2014/0227839 A1Published application

Method of manufacturing semiconductor device

AssigneeRenesas Electronics Corporation

InventorMasaaki SHINOHARA

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Abstract

Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

Claims20

Dependent claims

A method of manufacturing a semiconductor device comprising a memory cell of a nonvolatile memory formed in a semiconductor substrate located in a first region, and a MISFET formed in the semiconductor substrate located in a second region,

the memory cell including a first gate electrode, and a second gate electrode which are formed over the semiconductor substrate to be adjacent to each other, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and a second gate insulating film formed between the second gate electrode and the semiconductor substrate and having a charge storage portion therein,
the MISFET including a third gate electrode formed over the semiconductor substrate, and a third gate insulating film formed between the third gate electrode and the semiconductor substrate,
the method comprising the steps of:
(a) providing the semiconductor substrate;
(b) forming, over the semiconductor substrate located in the first region, the first gate electrode via the first gate insulating film, and the second gate electrode via the second gate insulating film;
(c) forming, over the semiconductor substrate, a first insulating film so as to cover the first gate electrode and the second gate electrode;
(d) polishing an upper surface of the first insulating film to planarize the upper surface of the first insulating film;
(e) after the step (d), forming, over the semiconductor substrate, a first conductive film for the third gate electrode so as to cover the first gate electrode, the second gate electrode, and the first insulating film;
(f) patterning the first conductive film to form the third gate electrode in the second region;
and
(g) after the step (f), removing the first insulating film.

8 more elements

the memory cell including a first gate electrode, and a second gate electrode which are formed over the semiconductor substrate to be adjacent to each other, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and a second gate insulating film formed between the second gate electrode and the semiconductor substrate and having a charge storage portion therein,
the MISFET including a third gate electrode formed over the semiconductor substrate, and a third gate insulating film formed between the third gate electrode and the semiconductor substrate, the method comprising the steps of:
(a) providing the semiconductor substrate;
(b) forming, over the semiconductor substrate located in the first region, the first gate electrode via the first gate insulating film, and the second gate electrode via the second gate insulating film;
(c) forming, over the semiconductor substrate, a first insulating film so as to cover the first gate electrode and the second gate electrode;
(d) polishing an upper surface of the first insulating film to planarize the upper surface of the first insulating film;
(e) after the step (d), forming, over the semiconductor substrate, a first film including a first conductive film so as to cover the first gate electrode, the second gate electrode, and the first insulating film;
(f) patterning the first film to form a dummy gate electrode for forming the third gate electrode in the second region;
(g) after the step (f), removing the first insulating film;
(h) after the step (g), forming, over the semiconductor substrate, a second insulating film so as to cover the first gate electrode, the second gate electrode, and the dummy gate electrode;
(i) polishing an upper surface of the second insulating film to expose the dummy gate electrode;
(j) after the step (i), removing at least one part of the dummy gate electrode;
and
(k) embedding a second conductive film in a region from which the dummy gate electrode has been removed in the step (j) to form the third gate electrode.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/085,825Filed 21 Nov 2013
Priority: JP 2013-02500512 Feb 2013
Published: 14 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/037
Of data-storage electrodes: comprising charge-trapping insulators
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region