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US 2014/0227829 A1Published application
Using interrupted through-silicon-vias in integrated circuits adapted for stacking
AssigneeConversant Intellectual Property Management Inc.
InventorPeter GILLINGHAM
Life of this patent
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Abstract
In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.
Claims16
A method of producing an integrated circuit, comprising:
- providing a substrate;
- providing on said substrate an active circuit and interconnect layer including a plurality of constituent metal layers;
- providing a plurality of vias extending through said substrate from said active circuit and interconnect layer to a surface of said substrate opposite said active circuit and interconnect layer;
- providing a plurality of bond pads on said surface and respectively axially aligned with said vias;
- electrically connecting said bond pads to said vias;
- providing a plurality of terminals on said active circuit and interconnect layer and respectively axially aligned with said vias;
- electrically connecting a first subset of said terminals to the associated vias;
- and
- providing a second subset of said terminals including one said terminal that is an electrically distinct node relative to the associated axially aligned via.
6 more elements
A method of producing an integrated circuit stack, comprising:
- producing a plurality of integrated circuits, including, for each integrated circuit
- providing a substrate,
- providing on said substrate an active circuit and interconnect layer including a plurality of constituent metal layers,
- providing a plurality of vias extending through said substrate from said active circuit and interconnect layer to a surface of said substrate opposite said active circuit and interconnect layer,
- providing a plurality of bond pads on said surface and respectively axially aligned with said vias,
- electrically connecting said bond pads to said vias,
- providing a plurality of terminals on said active circuit and interconnect layer and respectively axially aligned with said vias,
- electrically connecting a first subset of said terminals to the associated vias, and
- providing a second subset of said terminals including one said terminal that is an electrically distinct node relative to the associated axially aligned via;
- stacking said integrated circuits one upon another;
- and
- electrically connecting said terminals of one said integrated circuit to the respective bond pads of another said integrated circuit that is adjacent said one integrated circuit in said stack.
9 more elements
Dependencies are inferred from the claim text.