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US 2014/0225654 A1Published application
Phase-lock loop
AssigneeInfineon Technologies AG
InventorsChin Yeong KOH, Kar Ming YONG
Life of this patent
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Abstract
A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency.
Claims18
A phase-lock loop, comprising:
- an input for receiving a reference signal;
- an oscillator to receive a control signal and to generate an output signal;
- a frequency divider coupled to receive the output signal of the oscillator and being configured to divide down a frequency of the output signal of the oscillator by a factor, defining a divided down signal;
- a frequency detector coupled to receive the output signal of the oscillator and to receive a reference signal and configured to generate a comparison signal based on a comparison of frequencies of the reference signal and the output signal of the oscillator;
- a phase detector coupled to receive the divided down signal and further coupled to receive the reference signal, and configured to generate an output signal based on a comparison of the phases of the divided down signal and the reference signal;
- a loop filter coupled to receive the comparison signal and to receive the output signal of the phase detector and configured to generate the control signal based upon the comparison signal and the output signal of the phase detector, with the control signal altering the output signal.
3 more elements
A device, comprising:
- an oscillator to receive a control signal and having an output to provide an output signal that is dependent on the control signal;
- a frequency detector having a first input coupled to the output of the oscillator and a second input to receive a reference signal, the frequency detector to compare the output signal with the reference signal and to provide frequency difference signal at an output of the frequency detector;
- and
- a loop filter to receive the frequency difference signal, the loop filter to generate the control signal base at least in part on the frequency difference signal.
1 more element
A method, comprising:
- comparing an output signal with a reference signal, the comparing comprising:
- counting falling edges associated with one or more signals in a predetermined time period and summing to define a count output;
- comparing the count output with a product and a factor to define a comparison;
- generating a control signal based upon the comparison.
1 more element
A phase-lock loop, comprising:
- an oscillator to generate an output signal having a phase;
- a frequency detector coupled to receive the output signal of the oscillator, the frequency detector configured to:
- detect at least one falling edge of the output signal;
- increase a count for each falling edge detected;
- detect a falling edge of a reference signal;
- define a count summation related to a number of phases associated with the output signal;
- and
- compare the count summation with a product of a number of phases of the output signal and a factor, defining a comparison signal;
- and
- a loop filter coupled to receive the comparison signal and configured to generate a control signal based upon the comparison signal, with the control signal altering the output signal.
7 more elements
Dependencies are inferred from the claim text.