Phase interpolation circuit and receiver circuit

A receiver circuit comprising:

• a receiver configured to acquire data from a received signal in accordance with a clock signal;
• a detection circuit configured to detect a phase difference between the received signal and the clock signal on the basis of the data;
• and
• a phase interpolation circuit configured to adjust a phase of the clock signal on the basis of the phase difference,
• the phase interpolation circuit including:
• a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals;
• a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals;
• and
• a third circuit configured to generate the clock signal by combining the first intermediate signal and the second intermediate signal.