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US 2014/0211894 A1Published application
Data interface synchronization
AssigneeIntel Corporation
InventorWei-Lien Yang
Life of this patent
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Abstract
In one embodiment, an apparatus may include a de-serializer to convert serial data to parallel data, and a counter to provide an update signal based on a bit count of the serial data. The apparatus may further include a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal. The apparatus may further include an output unit to provide a validation indicator in response to the synchronization signal.
Claims30
An apparatus comprising:
- a de-serializer to convert serial data to parallel data;
- a counter to provide an update signal based on a bit count of the serial data;
- a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal;
- and
- an output unit to provide a validation indicator in response to the synchronization signal.
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A system comprising:
- a system on a chip comprising at least one core having at least one execution unit and receiver logic, the receiver logic comprising:
- a de-serializer to convert serial data to parallel data;
- a synchronizer to determine whether the parallel data is synchronized with a clock signal of the at least one core;
- and
- a wireless device coupled to the system on the chip via an interconnect, the interconnect used to communicate data between the wireless device and the receiver logic of the system on the chip.
2 more elements
A method comprising:
- de-serializing serial data to obtain parallel data of width N;
- providing an update signal for every N bits of the serial data;
- and
- determining whether a target clock signal is synchronized with the update signal.
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Dependencies are inferred from the claim text.