High frequency synchronizer
AssigneeQUALCOMM Incorporated
InventorsSeid Hadi Rasouli, Animesh Datta, Saravanan Marimuthu, Ohsang Kwon
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Abstract
Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.
Claims27
A circuit for resolving a metastable state in a synchronizer, comprising:
- a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal;
- and
- a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.
A method for resolving a metastable state in a synchronizer, comprising:
- delaying a data signal at a node in the synchronizer to produce a delayed data signal;
- and
- coupling the delayed data signal to the node after a delay from a first edge of a clock signal.
An apparatus for resolving a metastable state in a synchronizer, comprising:
- means for delaying a data signal at a node in the synchronizer to produce a delayed data signal;
- and
- means for coupling the delayed data signal to the node after a delay from a first edge of a clock signal.
Dependencies are inferred from the claim text.