Semiconductor Device Performing Stress Test

A semiconductor device comprising:

• a plurality of memory cell mats arranged in a first direction and each including a plurality of word lines extending in a second direction that is different from the first direction;
• a plurality of sense amplifier arrays each arranged between two memory cell mats adjacent to each other in the first direction;
• and
• an access control circuit that controls the sense amplifier arrays and the word lines, wherein
• the plurality of memory cell mats are classified into a plurality of units each including two or more memory cell mats arranged adjacently,
• when a test signal is not activated, the access control circuit selects any one of the units based on a first portion of a row address, and selects any one of the word lines included in selected one of the units based on a second portion of the row address, and
• when the test signal is activated, the access control circuit selects all of the units by degrading the first portion of the row address, and selects ones of the plurality of word lines included in each unit by degrading a portion of the second portion of the row address.