Process variation skew in an sram column architecture

A method for determining a degree of process variation skew between a plurality of bit cells within a static random-access-memory (SRAM) column architecture, the method comprising:

• setting a pre-charge circuit to equalize each of the plurality of bit cells to a bit line voltage;
• reading a first output of a first bit cell;
• adjusting, using a digital-to-analog converter (DAC), the bit line voltage to modify an output of the first bit cell until a second output of the first bit cell is opposite that of the first output;
• and
• storing the adjusted bit line voltage for the first bit cell.

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a plurality of bit cells within a static random access memory (SRAM) column architecture;
• a digital-to-analog converter (DAC) connected to the bit cells through a pair of multiplexers;
• and
• a pre-charge circuit connected to the bit cells through the pair of multiplexers,
• wherein the DAC and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells.