Boosted read write word line

A boosted control block, comprising:

• a delay module connected to at least one of a boosted read enabled pulse (RENP) line or a boosted write enabled pulse (WENP) line;
• a first NAND gate comprising a first NAND input, a second NAND input, and a first NAND output, the first NAND input connected to the delay module, the second NAND input connected to at least one of the RENP line or the WENP line;
• a first inverter comprising a first inverter input and a first inverter output, the first inverter input connected to the first NAND output, the first inverter output configured to generate a first word line signal at the first inverter output;
• a second inverter comprising a second inverter input and a second inverter output, the second inverter input connected to the first inverter output;
• a third inverter comprising a third inverter input and a third inverter output, the third inverter input connected to the second inverter output;
• and
• a coupled capacitor connected to the third inverter output, the coupled capacitor configured to generate a second boosted word line signal.

A method for enhancing performance associated with a two port synchronous random access memory (SRAM) bit cell array, comprising:

• applying a boosted word line signal to at least one of a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array, the boosted word line signal comprising a first stage and a second stage:
• the first stage associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level;
• and
• the second stage associated with a second stage voltage level above the Vdd voltage level.