Nonvolatile Logic Array with Built-In Test Drivers

A system on chip (SoC) comprising a memory array, wherein the memory array comprises:

• n rows by m columns of bit cells, wherein each of the bit cells is configured to store a bit of data;
• m bit lines each coupled to a corresponding one of the m columns of bit cells;
• m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit, wherein the m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and wherein the m drivers are operable to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits;
• wherein each of the m drivers further comprise a transfer gate configured to transfer an offset voltage into a sense node of the bitcell during a read access in response to a control signal.

A system on chip (SoC) comprising a memory array, wherein the memory array comprises:

• n rows by m columns of bit cells, wherein each of the bit cells is configured to store a bit of data;
• m bit lines each coupled to a corresponding one of the m columns of bit cells;
• m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit, wherein the m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and wherein the m drivers are operable to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits;
• further comprising:
• an AND gate having n inputs each coupled to a corresponding one of the m bit lines, the AND gate having an output line coupled to an input of a test controller on the SoC;
• and
• an OR gate having n inputs each coupled to a corresponding one of the m bit lines, the OR gate having an output line coupled to an input of the test controller.

A method for testing a memory array having n rows by m columns of bit cells within a system on a chip (SoC), the method comprising:

• writing all ones to a row of bit cells by asserting a control signal to a write ones circuit included within a set of bit line drivers of the memory array;
• reading the row of bit cells;
• determining if all of the bit cells in the row contain a one;
• writing all zeros to the row of bit cells by asserting a control signal to a write zeros circuit included within the set of bit line drivers of the memory array;
• reading the row of bit cells;
• and
• determining if all of the bit cells in the row contain a zero;
• wherein determining if all of the bit cells in the row contain a one is performed by testing the output of an AND gate having n inputs each coupled to a corresponding one of the m columns of bit cells to determine if all of the bit cells in the row contain a one;
• and
• wherein determining if all of the bit cells in the row contain a zero is performed by testing the output of an OR gate having n inputs each coupled to a corresponding one of the m columns of bits cells to determine if all of the bit cells in the row contain a zero.

A method for testing a memory array having n rows by m columns of bit cells within a system on a chip (SoC), the method comprising:

• writing all ones to a row of bit cells by asserting a control signal to a write ones circuit included within a set of bit line drivers of the memory array;
• reading the row of bit cells;
• determining if all of the bit cells in the row contain a one;
• writing all zeros to the row of bit cells by asserting a control signal to a write zeros circuit included within the set of bit line drivers of the memory array;
• reading the row of bit cells;
• and
• determining if all of the bit cells in the row contain a zero;
• further comprising:
• removing power from the memory array after writing all ones or all zeros to a row of bit cells;
• baking the memory array at an elevated temperature for a period of time;
• restoring power to the memory array and then reading the row of bit cells and determining if all of the bit cells in the row contain a one or determining if all of the bit cells in the row contain a zero.

A method for testing a memory array having n rows by m columns of bit cells within a system on a chip (SoC), the method comprising:

• writing all ones to a row of bit cells by asserting a control signal to a write ones circuit included within a set of bit line drivers of the memory array;
• reading the row of bit cells;
• determining if all of the bit cells in the row contain a one;
• writing all zeros to the row of bit cells by asserting a control signal to a write zeros circuit included within the set of bit line drivers of the memory array;
• reading the row of bit cells;
• and
• determining if all of the bit cells in the row contain a zero;
• further comprising applying an offset voltage to each bitcell in the row via a pass gate included within a set of bit line drivers of the memory array while reading the row of bit cells.