Voltage divider control circuit

A write assist circuit, comprising:

• a voltage divider comprising:
• an output;
• a pull up unit;
• a pull down unit;
• and
• a header unit;
• a memory cell array connected to the output of the voltage divider;
• and
• a control circuit configured to at least one of:
• bias the pull up unit of the voltage divider using an analog signal associated with a Vppu voltage level;
• or
• bias the pull up unit of the voltage divider a delay time (Tppu) after the pull down unit of the voltage divider is biased.

A method for controlling a voltage divider, comprising:

• biasing a pull up gate of a pull up unit of a voltage divider logic high during a first stage;
• biasing a pull down gate of a pull down unit of the voltage divider logic low during the first stage;
• biasing a header gate of a header unit of a voltage divider logic high during the first stage;
• biasing the pull up gate to a Vppu voltage level during a second stage;
• biasing the pull down gate logic low during the second stage;
• and
• biasing the header gate logic high during the second stage.