Nonvolatile Logic Array with Built-In Test Result Signal
AssigneeTexas Instruments Incorporated
InventorsSteven Craig Bartling, Sudhanshu Khanna
Life of this patent
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Abstract
A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.
Claims15
A system on chip (SoC) comprising a memory array, wherein the memory array comprises:
- n rows by m columns of bit cells, wherein each of the bit cells is configured to store a bit of data;
- m bit lines each coupled to a corresponding one of the m columns of bit cells;
- m write drivers each coupled to a corresponding one of the m bit lines;
- an AND gate having n inputs each coupled to a corresponding one of the m bit lines, the AND gate having an output line;
- and
- an OR gate having n inputs each coupled to a corresponding one of the m bit lines, the OR gate having an output line.
A method for testing a memory array having n rows by m columns of bit cells within a system on a chip (SoC), the method comprising:
- writing all ones to a row of bit cells;
- reading the row of bit cells;
- testing the output of an AND gate having n inputs each coupled to a corresponding one of the m columns of bit cells to determine if all of the bit cells in the row contain a one;
- writing all zeros to the row of bit cells
- reading the row of bit cells;
- and
- testing the output of an OR gate having n inputs each coupled to a corresponding one of the m columns of bits cells to determine if all of the bit cells in the row contain a zero.
Dependencies are inferred from the claim text.