Adjustment of Write Timing in a Memory Device
AssigneeAdvanced Micro Devices, Inc.
InventorsMing-Ju Edward LEE, Shadi M. BARAKAT, Warren Fritz KRUGER, Xiaoling XU, Toan Duc PHAM, Aaron John NYGREN
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Abstract
A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.
Claims10
A method for adjusting a write timing in a memory device, comprising:
- sending at data signal, a write clock signal, and as reference signal to the memory device;
- receiving a sampled reference signal from the memory device;
- computing phase measurements of the sampled reference signal over at period of time;
- comparing the computed phase measurements of the sampled reference signal over the period of time;
- computing is phase error signal based on the compared phase measurements;
- and
- adjusting a phase difference between the data signal and the write clock signal based on the phase error signal, the adjusting comprising:
- sampling the sampled reference signal;
- detecting a phase of the sampled reference signal;
- and
- comparing the phase of the sampled reference signal over the period of time to adjust the phase difference.
A system configured to adjust a writing timing in a memory device, the system comprising:
- a memory device configured to:
- receive a data signal, a write dock signal, and a reference signal,
- sample the reference signal,
- recover data from the data signal based on a write timing of the data signal and the write clock signal,
- compute phase measurements of the sampled reference signal over a period of time,
- compare the computed phase measurements of the sampled reference signal over the period of time, and
- generate a phase shift based on the compared phase measurements over the period of time;
- and
- a processing unit configured to
- transmit the data signal, write clock signal, and the reference signal to the memory device,
- receive the sampled reference signal from the memory device,
- compute a phase error signal based on the compared phase measurements and the phase shift, and
- adjust a phase difference between the data signal and the write clock signal based on the phase error signal.
A system configured to adjust a write timing in a memory device, comprising:
- a processing unit configured to transmit a data signal, a write clock signal, and a reference signal to a memory device;
- and
- the memory device configured to
- recover data from the data signal based on a write timing of the data signal and the write clock signal,
- sample the reference signal, and
- to transmit, to the processing unit, information corresponding to a phase difference between the data signal and the write clock signal based on computed phase measurements of the sampled reference signal over a period of time and a phase shift based on the compared phase measurements.
The system of claim 10, wherein the processing unit is configured to adjust a phase difference between the data signal and the write clock signal based on the information transmitted from the memory device.
Dependencies are inferred from the claim text.