Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorFumihiro KONO
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory device includes a first sense amplifier that is located in a first region and amplifies signals from a memory cell in the first region. A second sense amplifier is located in a second region and amplifies signals from a memory cell in the second region. A bus is connected to the first and second sense amplifiers and passes through the first and second regions. A first latch is located in the second region and is connected to the bus. A second latch is located in the second region and is connected to the bus.
Claims20
A semiconductor memory device comprising:
- a first sense amplifier that is positioned in a first region and amplifies signals from a memory cell in the first region;
- a second sense amplifier that is positioned in a second region and amplifies signals from a memory cell in the second region;
- a bus that is connected to the first and second sense amplifiers and passes through the first and second regions;
- a first latch that is positioned in the second region and is connected to the bus, and
- a second latch that is positioned in the second region and is connected to the bus.
A semiconductor memory device comprising:
- a plurality of memory cells including a plurality of planes therein;
- a data bus extending in communication with at least two of the plurality of planes;
- and
- within the at least two of the plurality of planes, a plurality of bit lines and a plurality of sense amplifiers, each bit line selectively connectable to the plurality of sense amplifiers at a first side thereof, wherein the second side of the sense amplifiers is connected to the data bus extending in communication with at least two of the plurality of planes.
A method of configuring a semiconductor memory device, comprising:
- providing a first plane of the memory including a plurality of bit lines interconnected with a plurality of sense amplifiers;
- providing a second plane of the memory including a plurality of bit lines interconnected with a plurality of sense amplifiers;
- providing a data bus configured to interconnect to the first plane and the second plane.
Dependencies are inferred from the claim text.