Programming a split gate bit cell
AssigneeFreescale Semiconductor, Inc.
InventorsCheong M. Hong, Ronald J. Syzdek, Brian A. Winstead
Life of this patent
Estimating the term…
Loading patent…
AssigneeFreescale Semiconductor, Inc.
InventorsCheong M. Hong, Ronald J. Syzdek, Brian A. Winstead
Estimating the term…
A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.
In a split gate memory having a first sector of split gate memory cells arranged in rows and columns, wherein each split gate memory cell has a control gate, a select gate coupled to a word line along one of the rows, a drain terminal coupled to a bit line along one of the columns, and a source terminal, a method of selective programming, comprising:
A split gate memory, comprising:
A method for selectively programming a split gate memory, comprising:
Dependencies are inferred from the claim text.