Signal processing circuit

A signal processing circuit comprising a plurality of memory cells each comprising:

• a first word line and a second word line;
• a first data line and a second data line;
• a first transistor comprising an oxide semiconductor in a channel formation region;
• a second transistor;
• and
• a memory element to which charge whose amount depends on a value of data is supplied via the first transistor,
• wherein a gate of the first transistor is electrically connected to the first word line and one of source and drain of the first transistor is electrically connected to the first data line, and
• wherein a gate of the second transistor is electrically connected to the second word line, one of source and drain of the second transistor is electrically connected to the second data line, and the other of source and drain of the second transistor is electrically connected to the memory element.

A signal processing circuit comprising a plurality of memory cells each comprising:

• a first word line and a second word line;
• a first data line and a second data line;
• a first transistor comprising an oxide semiconductor in a channel formation region;
• and
• a second transistor;
• wherein a gate of the first transistor is electrically connected to the first word line, one of source and drain of the first transistor is electrically connected to the first data line, the other of source and drain of the first transistor is electrically connected to a first gate of the second transistor, and
• wherein a second gate of the second transistor is electrically connected to the second word line, one of source and drain of the second transistor is electrically connected to the second data line, and the other of source and drain of the second transistor is electrically connected to a node to which a predetermined potential is applied.

A signal processing circuit comprising a plurality of memory cells each comprising:

• a word line;
• a first data line and a second data line;
• a first transistor comprising an oxide semiconductor in a channel formation region;
• a second transistor;
• and
• a memory element to which charge whose amount depends on a value of data is supplied via the first transistor,
• wherein a gate of the first transistor is electrically connected to the word line and one of source and drain of the first transistor is electrically connected to the first data line, and
• wherein a gate of the second transistor is electrically connected to the word line, one of source and drain of the second transistor is electrically connected to the second data line, and the other of source and drain of the second transistor is electrically connected to the memory element.