Mram self-repair with bist logic
AssigneeQUALCOMM Incorporated
InventorsJung Pill Kim, Taehyun Kim, Xia Li, Seung H. Kang
Life of this patent
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Abstract
Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.
Claims28
A memory comprising:
- a memory cell array on a chip;
- a built-in self test (BIST) circuit on the chip and coupled to the memory cell array, the BIST circuit configured to perform a write operation to write addresses of failed memory cells in the memory cell array to a failed address sector in the memory cell array;
- and
- a first select circuit coupled between the BIST circuit and the memory cell array, the first select circuit configured to selectively couple an output of the BIST circuit and an input to the memory cell array.
A method for memory self repair, comprising:
- performing a built-in self test (BIST) process by BIST circuitry on a chip to identify addresses of failed memory cells in a memory cell array on the chip;
- and
- transferring the addresses of the failed memory cells directly from the BIST circuitry to a portion of the memory cell array.
An apparatus for memory self repair comprising:
- means for performing a built-in self test (BIST) process to identify addresses of failed memory cells in a memory cell array on the chip;
- and
- means for transferring the addresses of the failed memory cells directly from the BIST circuitry to a portion of the memory cell array.
A method for memory self repair, comprising steps of:
- performing a built-in self test (BIST) process by BIST circuitry on a chip to identify addresses of failed memory cells in a memory cell array on the chip;
- and
- transferring the addresses of the failed memory cells directly from the BIST circuitry to a portion of the memory cell array.
Dependencies are inferred from the claim text.