US 2014/0211549 A1 · ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY

Abstract

A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.

Claims20

Dependent claims

A magnetoresistive memory apparatus, comprising:

plural bit cells, each bit cell having at least one magnetoresistive element characterized by different resistances in different logic states of the bit cell, and each said bit cell occupying a bit cell position in a memory array having plural memory words, each memory word being addressable by a word line signal during a memory access operation involving one of reading from and writing to bit cells in the memory word;
a read-write circuit for the bit cell position, the read/write circuit having one of an input and an output coupled to a bit line, and the bit cell being coupled between the bit line and a source line by at least one switching transistor when the bit cell is addressed during the memory access operation, such that relative lengths of the bit line and the source line vary oppositely as a function of a location of the bit cell in the memory array;
a drive control coupled to vary an input to the switching transistor as a function of relative resistance of the bit line and the source line.

A magnetoresistive random access memory, comprising:

a memory array containing magnetoresistive bit cells occupying bit positions in addressable word lines, each of the bit cells comprising at least one magnetic tunnel junction and a bit cell switching transistor operable to couple the bit cell between a bit line and a source line for an associated bit position during a read operation enabled by applying a drive signal to a clamping switching transistor for coupling the bit line to a sensing circuit, the bit line and the source line leading to a current source for applying a reading current at a reading current amplitude to the bit cell when addressed at least during the read operation;
wherein the bit line and the source line have characteristic resistances as a function of length, and the bit cells are coupled between the bit line and the source line at longer and shorter distances from the sensing circuit and the current source, as a function of a location in the array of addressable word line containing the bit cell in the array;
a sensing circuit operable to discern a logic value stored in the bit cell by detecting one of a relatively higher resistance RH state and a relatively lower resistance RL state of the bit cell while applying the reading current amplitude through the clamping switching transistor;
wherein at least the clamping reference switching transistor is coupled to a variable drive control configured to supply a higher and lower drive signal as a function of the location of the word line in the array.

1 more element

Dependencies are inferred from the claim text.

Accommodating balance of bit line and source line resistances in magnetoresistive random access memory

Life of this patent

Accommodating balance of bit line and source line resistances in magnetoresistive random access memory

Life of this patent

Abstract

Claims20