Low power static random access memory
AssigneeRaytheon Company
InventorsMICKY HARRIS, WASIM KHALED
Life of this patent
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Abstract
A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.
Claims20
A bit line driver for a static random access memory (SRAM) cell comprising:
- a first voltage supply for supplying a first voltage;
- a second voltage supply for supplying a second voltage that is less than the first voltage;
- a write circuit configured to drive a bit line and an inverse bit line when writing to the SRAM cell;
- and
- a pre-charge circuit configured to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell,
- wherein the bit line driver is configured to supply a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.
A static random access memory (SRAM) array comprising:
- a plurality of word lines arranged in rows, each of the word lines for supplying a corresponding one of a plurality of word signals;
- a plurality of bit lines arranged in columns, each of the bit lines for supplying a corresponding one of a plurality of bit signals;
- a plurality of inverse bit lines arranged with the bit lines in columns, each of the inverse bit lines for supplying a corresponding one of a plurality of inverse bit signals that is the inverse of the bit signal supplied by the corresponding one of the bit lines in a same column;
- a first voltage supply for supplying a first voltage;
- a second voltage supply for supplying a second voltage that is less than the first voltage;
- a plurality of SRAM cells arranged in rows and columns, each of the SRAM cells corresponding to one of each of the word lines, the bit lines, and the inverse bit lines;
- a word line driver configured to drive the word lines;
- and
- a bit line driver configured to drive the bit lines and the inverse bit lines,
- wherein the bit line driver is configured to supply a voltage less than the first voltage by a threshold voltage of one transistor of the bit line driver to the one of the bit lines when the bit line driver drives one of the bit lines to a high state, and
- wherein the bit line driver is configured to supply the voltage less than the first voltage by a threshold voltage of one transistor of the bit line driver to the one of the inverse bit lines when the bit line driver drives one of the inverse bit lines to the high state.
Dependencies are inferred from the claim text.