Resistance-based random access memory

A resistance-based random access memory circuit comprising a plurality of memory column modules, each of the plurality of memory column modules comprising:

• a first data line comprising a first end, a second end, and N nodes defined between the first end of the first data line and the second end of the first data line, and N being an integer and 2≦N;
• a second data line comprising a first end, a second end, and N nodes defined between the first end of the second data line and the second end of the second data line;
• N resistance-based memory cells, each of the N resistance-based memory cells having a first end connected to one of the N nodes of the first data line, and a second end connected to one of the N nodes of the second data line corresponding to the one of the N nodes of the first data line;
• a first driving unit coupled with the first end of the first data line and the first end of the second data line;
• and
• a second driving unit coupled with the second end of the first data line and the second end of the second data line,
• wherein the first driving unit and the second driving unit are configured to create a conductive path passing through first X, counting from the first end of the first data line, of the N nodes of the first data line and (N−X+1), counting from the second end of the second data line, of the N nodes of the second data line, X being an integer and 1≦x≦N.

A method of operating a resistance-based random access memory circuit, the method comprising:

• setting a first driving unit to couple a first end of a first data line to a first voltage node and to decouple a first end of a second data line from the first voltage node;
• setting a second driving unit to decouple a second end of the first data line from a second voltage node and to couple a second end of the second data line to the second voltage node;
• and
• establishing a conductive path between the first data line and the second data line through one of a plurality of resistance-based memory cells of the memory circuit in response to a word line signal, the plurality of resistance-based memory cells being arranged in a column along the first data line and the second data line, each of the plurality of resistance-based memory cells having a first end coupled with the first data line and a second end coupled with the second data line.