US 2014/0211533 A1Published application

Two Capacitor Self-Referencing Nonvolatile Bitcell

AssigneeTexas Instruments Incorporated

InventorsSudhanshu Khanna, Steven Craig Bartling

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Abstract

A system on chip (SoC) provides a memory array of self referencing nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit coupled to the node Q. A first read capacitor is coupled to the bit line via a transfer device controlled by a first control signal. A second read capacitor coupled to the bit line via another transfer device controlled by a second control signal. A sense amp is coupled between the first read capacitor and the second read capacitor.

Claims15

Dependent claims

A system on chip (SoC) comprising:

a memory array of self referencing non-volatile bit cells, wherein each bit cell comprises:
two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors, wherein the first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed;
and
a transfer gate coupled between the node Q and a bit line;
wherein the memory array further comprises:
a first read capacitor coupled to the bit line via a transfer device controlled by a first control signal;
a second read capacitor coupled to the bit line via another transfer device controlled by a second control signal;
and
a sense amp coupled between the first read capacitor and the second read capacitor, the sense amp being operable to determine a value stored in a selected bit cell by comparing a first sense voltage transferred from the node Q to the first read capacitor by the first transfer device and a second sense voltage transferred from the node Q to the second read capacitor by the second transfer device.

6 more elements

A method for reading a bit cell in a memory array within a system on a chip (SoC), wherein the bit cell comprises two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors, the method comprising:

placing a first voltage on the first plate line and on the second plate line while the bit cell is not being accessed;
clamping the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed;
obtaining a first sense voltage from the node Q by unclamping the node Q, placing a second voltage on the first plate line while maintaining the first voltage on the second plate line, and transferring the first sense voltage from the node Q to a first read capacitor;
resetting the node Q by placing the first voltage on the first plate line while maintaining the first voltage on the second plate line and clamping the node Q to a voltage approximately equal to first voltage for a short period of time;
obtaining a second sense voltage by unclamping the node Q, placing a second voltage on the second plate line while maintaining the first voltage on the first plate line, and transferring the second sense voltage from the node Q to a second read capacitor;
and
determining a stored data value for the bit cell by comparing the first sense voltage to the second sense voltage.

4 more elements

Dependencies are inferred from the claim text.