Semiconductor integrated circuit device
AssigneePanasonic Corporation
InventorDaisuke MATSUOKA
Life of this patent
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Abstract
An ESD protection circuit includes a resistive element, a capacitive element, a protecting element, and a controller. The resistive element, the protecting element, and the controller are provided in an element formation layer. At least part of the capacitive element includes an interconnect capacitor provided in a plurality of interconnect layers. When viewed in plan, at least part of a capacitance formation region in which the interconnect capacitor is provided overlaps at least part of an element formation region in which the resistive element, the protecting element, and the controller are provided.
Claims12
A semiconductor integrated circuit device comprising:
- an ESD protection circuit;
- an element formation layer;
- and
- a plurality of interconnect layers above the element formation layer, wherein
- the ESD protection circuit includes
- a resistive element and a capacitive element connected in series between a first terminal and a second terminal of the ESD protection circuit,
- a protecting element connected between the first terminal and the second terminal, and
- a controller configured to control a conductive state of the protecting element in accordance with a potential at a connect node between the resistive element and the capacitive element,
- the resistive element, the protecting element, and the controller are provided in the element formation layer,
- at least part of the capacitive element includes an interconnect capacitor provided in the interconnect layers, and
- when viewed in plan, at least part of a capacitance formation region in which the interconnect capacitor is provided overlaps at least part of an element formation region in which the resistive element, the protecting element, and the controller are provided.
A semiconductor integrated circuit device comprising:
- an ESD protection circuit;
- an element formation layer;
- and
- a plurality of interconnect layers above the element formation layer, wherein
- the ESD protection circuit includes
- a resistive element and a capacitive element connected in series between a first terminal and a second terminal of the ESD protection circuit,
- a protecting element connected between the first terminal and the second terminal, and
- a controller configured to control a conductive state of the protecting element in accordance with a potential at a connect node between the resistive element and the capacitive element,
- the resistive element, the protecting element, and the controller are provided in the element formation layer,
- the capacitive element includes an interconnect capacitor provided in the interconnect layers and a MOS capacitor provided in the element formation layer, and
- when viewed in plan, at least part of a capacitance formation region in which the interconnect capacitor is provided overlaps at least part of an element formation region in which the resistive element, the protecting element, the controller, and the MOS capacitor are provided.
Dependencies are inferred from the claim text.