Phase Locked Loop and Method for Operating the Same

A phase locked loop (PLL) comprising:

• a phase frequency detector (PFD) adapted to receive a feedback clock (SYSCLK) and a reference clock (REFCLK) and adapted to provide UP pulses and DOWN pulses for controlling the oscillation frequency of a controlled oscillator (VCO) in response to a phase and/or frequency difference between the feedback clock and the reference clock;
• a first charge pump (CP1) adapted to receive the UP pulses and DOWN pulses from the phase frequency detector (PFD), wherein the first charge pump (CP1) is further adapted to provide a first analog control signal (ICH) to a first control input (PROP) of a controlled oscillator (VCO) to control its oscillation frequency in response to the UP pulses and DOWN pulses from the phase frequency detector (PFD),
• a second charge pump (CP2) adapted to receive the UP pulses and DOWN pulses from the phase frequency detector (PFD), wherein the second charge pump (CP2) is further adapted to provides a first analog storage control signal (FAST) and a second analog storage control signal (SLOW) corresponding to the UP pulses and DOWN pulses from the phase frequency detector (PFD) to a control stage (DCONT);
• said control stage (DCONT) adapted to provide a second analog control signal (D) to a second control input (VSUP) of the controlled oscillator (VCO) to control its oscillation frequency in response to the first analog storage control signal (FAST) and a second analog storage control signal (SLOW);
• said controlled oscillator (VCO) adapted to output an output signal (OUTVCO) with a desired oscillation frequency in response to the first analog control signal (ICH) received at the first control input (PROP) and the second analog control signal (D) to the second control input (VSUP);
• and
• a feedback loop adapted to feedback the output signal (OUTVCO) of the controlled oscillator (VCO) to the input of the phase frequency detector (PFD) as said feedback clock (SYSCLOCK),
• wherein first charge pump (CP1) and/or the second charge pump (CP2) are adapted to receive the output signal (OUTVCO) of the controlled oscillator (VCO) and to use the same for process-voltage-temperature (PVT) compensation,
• wherein the first charge pump (CP1) is adapted to increase or decrease the amount of current provided by the first analog control signal (ICH) in response to the output signal (OUTVCO) of the controlled oscillator (VCO).

A method for operating a phase locked loop (PLL) comprising:

• receiving a feedback clock (SYSCLK) and a reference clock (REFCLK) at a phase frequency detector (PFD);
• providing UP pulses and DOWN pulses for controlling the oscillation frequency of a controlled oscillator (VCO) in response to a phase and/or frequency difference between the feedback clock and the reference clock;
• receiving the UP pulses and DOWN pulses at a first charge pump (CP1);
• providing a first analog control signal (ICH) from the first charge pump (CP1) to a first control input (PROP) of a controlled oscillator (VCO) to control its oscillation frequency;
• receiving the UP pulses and DOWN pulses at a second charge pump (CP2);
• providing a first analog storage control signal (FAST) and a second analog storage control signal (SLOW) corresponding to the UP pulses and DOWN pulses to a control stage (DCONT);
• providing by said control stage (DCONT) a second analog control signal (D) to a second control input (VSUP) of the controlled oscillator (VCO) to control its oscillation frequency in response to the first analog storage control signal (FAST) and a second analog storage control signal (SLOW);
• outputting, by said controlled oscillator (VCO), an output signal (OUTVCO) with a desired oscillation frequency in response to the first analog control signal (ICH) and the second analog control signal (D) to the second control input (VSUP);
• and
• continuously charging and resetting, or discharging and resetting, storage elements (S1, S2) of the control stage in respective cycles and in response to the first analog storage control signal (FAST) and a second analog storage control signal (SLOW), respectively;
• increasing or decreasing a counter value of a digital counter in response to the number of charging cycles or discharging cycles performed by the storage elements (S1, S2), respectively;
• convert the digital counter value of the counter to a control current;
• superimposing the control current with currents representing the respective charging/discharging state of the respective two storage elements;
• and
• providing the superimposed current as the second analog control signal (D) to the second control input (VSUP) to the controlled oscillator (VCO).

A method for operating a phase locked loop (PLL) comprising:

• receiving a feedback clock (SYSCLK) and a reference clock (REFCLK) at a phase frequency detector (PFD);
• providing UP pulses and DOWN pulses for controlling the oscillation frequency of a controlled oscillator (VCO) in response to a phase and/or frequency difference between the feedback clock and the reference clock;
• receiving the UP pulses and DOWN pulses at a first charge pump (CP1);
• providing a first analog control signal (ICH) from the first charge pump (CP1) to a first control input (PROP) of a controlled oscillator (VCO) to control its oscillation frequency;
• receiving the UP pulses and DOWN pulses at a second charge pump (CP2);
• providing a first analog storage control signal (FAST) and a second analog storage control signal (SLOW) corresponding to the UP pulses and DOWN pulses to a control stage (DCONT);
• providing by said control stage (DCONT) a second analog control signal (D) to a second control input (VSUP) of the controlled oscillator (VCO) to control its oscillation frequency in response to the first analog storage control signal (FAST) and a second analog storage control signal (SLOW);
• outputting, by said controlled oscillator (VCO), an output signal (OUTVCO) with a desired oscillation frequency in response to the first analog control signal and the second analog control signal (D) to the second control input (VSUP);
• receiving the output signal (OUTVCO) of the controlled oscillator (VCO) at the first charge pump (CP1) and/or the second charge pump (CP2) and
• using the output signal (OUTVCO) of the controlled oscillator (VCO) for process-voltage-temperature (PVT) compensation,
• wherein the first charge pump (CP1) is adapted to increase or decrease the amount of current provided by the first analog control signal (ICH) in response to the output signal (OUTVCO) of the controlled oscillator (VCO).