Level Shifter Circuit Optimized for Metastability Resolution and Integrated Level Shifter and Metastability Resolution Circuit

An integrated circuit comprising:

• a first circuit in a first power domain, wherein the first power domain is within a with a first clock domain;
• a level shifter in a second power domain, wherein the level shifter circuit is coupled to receive, from the first circuit, a differential input signal having a true logic value and a complementary logic value, wherein the level shifter includes:
• a storage circuit configured to store the true and complementary values of the differential input signal;
• and
• an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal;
• and
• a latch circuit in a second clock domain coinciding with the second power domain, wherein the latch circuit is coupled to receive the true and complementary output logic signals and further coupled to receive a pulse clock signal, wherein the latch circuit is configured to latch data according to the true and complementary output logic signals responsive to receiving an active pulse of the pulse clock signal, and further configured to provide a single-ended output logic signals based on the latched data.