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US 2014/0210515 A1Published application
Pld architecture for flexible placement of ip function blocks
AssigneeAltera Corporation
InventorsAndy L. Lee, Cameron R. McClintock, Brian D. Johnson, Richard G. Cliff, Srinivas T. Reddy, Christopher F. Lane, Paul Leventis, Vaughn Betz, David Lewis
Life of this patent
Estimating the term…
Abstract
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
Claims21
1-37. (canceled)
A programmable logic device, comprising:
- a logic element (LE) array;
- a base signal routing architecture including a plurality of signal routing lines to route signals among the LE array;
- and
- an interface region for interconnecting an IP function block and the LE array, the interface region comprising interfacing circuitry for selectively applying a signal provided by the base signal routing architecture to the IP function block.
1 more element
A semiconductor integrated circuit, comprising:
- a logic element (LE) array;
- a base signal routing architecture including a plurality of signal routing lines to route signals among the LE array;
- and
- an interface region for interconnecting an IP function block and the LE array, the interface region comprising interfacing circuitry for selectively applying a signal provided by the base signal routing architecture to the IP function block.
1 more element
A programmable logic device, comprising:
- a logic element (LE) array;
- and
- an interface region for interconnecting an IP function block and the LE array, the interface region comprising interfacing circuitry for selectively applying a signal provided by a logic element in the LE array to the IP function block.
Dependencies are inferred from the claim text.