Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorJI-WOON PARK
Life of this patent
Estimating the term…
Abstract
A semiconductor package offers improved product reliability by supplying a power voltage and a ground voltage to a semiconductor chip in a secured manner using a redistribution layer (RDL) structure. The semiconductor package includes a first semiconductor chip disposed on a substrate, a second semiconductor chip disposed on the first semiconductor chip, a plurality of redistribution lines disposed on the first semiconductor chip and electrically connecting the first semiconductor chip to the second semiconductor chip, and a redistribution wire disposed on the first semiconductor chip and electrically connecting one of the redistribution lines to another.
Claims20
A semiconductor package comprising:
- at least one first semiconductor chip disposed on a substrate;
- a second semiconductor chip disposed on the at least one first semiconductor chip;
- redistribution lines extending on the at least one first semiconductor chip and providing conductive paths, respectively;
- each of which paths electrically connects the first semiconductor chip to the second semiconductor chip independently of the other;
- and
- at least one redistribution wire disposed on the at least one first semiconductor chip and electrically connecting a plurality of the redistribution lines to one another.
A semiconductor package comprising:
- a first semiconductor chip disposed on a substrate;
- a second semiconductor chip disposed on the first semiconductor chip;
- redistribution lines each disposed on the first semiconductor chip;
- and
- redistribution wires disposed on the first semiconductor chip and electrically connecting respective ones of the redistribution lines to one another,
- wherein the redistribution lines include a plurality of first redistribution lines electrically connecting the first semiconductor chip to the second semiconductor chip to supply a first voltage to the first semiconductor chip, a plurality of second redistribution lines electrically connected to the second semiconductor chip to supply the first voltage to the second semiconductor chip, and a plurality of third redistribution lines electrically connected to the second semiconductor chip to supply the first voltage to the second semiconductor chip,
- the redistribution wires include a first redistribution wire electrically connecting one of the first redistribution lines to another of the first redistribution lines, a second redistribution wire electrically connecting one of the second redistribution lines to another of the second redistribution lines, and third redistribution wires electrically connecting the first redistribution line, the second redistribution line and the third redistribution line to one another.
A multi-chip semiconductor device comprising:
- a first semiconductor chip including a first chip body having an upper surface at the top of the device;
- a second semiconductor chip stacked on the first semiconductor chip so as to also be located at the top of the device, the second semiconductor chip including a second chip body adhered to the first chip body;
- redistribution lines extending over the upper surface of the first chip body, the redistribution lines providing conductive paths, respectively, each of which paths electrically connects the first semiconductor chip to the second semiconductor chip independently of the other;
- and
- at least one redistribution wire running alongside the upper surface of the first chip body, each said at least one redistribution wire electrically connecting two of the redistribution lines to one another.
Dependencies are inferred from the claim text.