Stacked wafer ddr package
AssigneeApple Inc.
InventorJun Zhai
Life of this patent
Estimating the term…
Abstract
A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.
Claims25
A semiconductor device package, comprising:
- a first memory die at least partially encapsulated in an encapsulant with at least one surface of the first memory die exposed;
- a redistribution layer coupled to the exposed surface of the first memory die, wherein the redistribution layer comprises a single layer of routing, and wherein the single layer of routing comprises a first routing and a second routing that are electrically isolated;
- a second memory die coupled to the redistribution layer, wherein the second memory die is coupled on an opposing surface of the redistribution layer from the first memory die, and wherein the second memory die is offset from the first memory die;
- and
- a plurality of terminals coupled to the redistribution layer, wherein a first set of the terminals are coupled to the first memory die through the first routing in the redistribution layer and a second set of the terminals are coupled to the second memory die through the second routing in the redistribution layer.
(canceled)
(canceled)
A semiconductor device package, comprising:
- a mold material with a first memory die at least partially enclosed in the mold material;
- a redistribution layer coupled to a bottom surface of the mold material;
- a second memory die coupled to a bottom surface of the redistribution layer, wherein the second memory die is offset from the first memory die;
- and
- a plurality of terminals coupled to the bottom surface of the redistribution layer on a periphery of the first memory die and a periphery of the second memory die;
- wherein the redistribution layer comprises a single layer of routing, wherein the single layer of routing comprises a first routing and a second routing that are electrically isolated, and wherein the first routing couples the first memory die to a first set of the terminals and the second routing couples the second memory die to a second set of the terminals.
(canceled)
(canceled)
A method for forming a semiconductor device package, comprising:
- providing a first memory die at least partially encapsulated in an encapsulant with at least one surface of the first memory die exposed;
- coupling a redistribution layer to the first memory die, wherein the redistribution layer comprises a first routing and a second routing in a single layer of routing, and wherein the first routing and the second routing are electrically isolated;
- coupling a plurality of terminals to the redistribution layer, wherein a first set of the terminals are coupled to the first memory die through the first routing in the redistribution layer;
- and
- coupling a second memory die to the redistribution layer, wherein the second memory die is offset from the first memory die, and wherein a second set of the terminals are coupled to the second memory die through the second routing in the redistribution layer.
(canceled)
Dependencies are inferred from the claim text.