Conductive line routing for multi-patterning technology

A method, comprising:

• forming a first plurality of first reference voltage patterns in a first layer of a semiconductor substrate using a first mask;
• forming a first plurality of signal patterns in the first layer of the semiconductor substrate using a second mask between successive ones of the first plurality of first reference voltage patterns;
• forming a second plurality of first reference voltage patterns in a second layer of the semiconductor substrate using a third mask;
• forming a first plurality of vias using a first via mask, for connecting the first reference voltage patterns in the first layer to the first reference voltage patterns in the second layer, so that the vias are aligned along a plurality of straight diagonal lines passing through points where first reference voltage patterns of the second layer cross over first reference voltage patterns of the first layer.

A method, comprising:

• forming a first reference voltage pattern and a second reference voltage pattern in a first layer of a semiconductor substrate using a first mask;
• forming a signal pattern in the first layer of the semiconductor substrate using a second mask, the signal pattern located between the first reference voltage pattern and the second reference voltage pattern;
• and
• forming a respective via on each of the first reference voltage pattern, the second reference voltage pattern, and the signal pattern, along a diagonal line relative to the reference voltage pattern, the second reference voltage pattern, and the signal pattern.