Capping Layer for Improved Deposition Selectivity

A back-end-of-the-line (BEOL) layer of an integrated chip, comprising:

• a first etch stop layer disposed over a semiconductor substrate;
• an extreme low-k (ELK) dielectric layer comprising a lower ELK dielectric layer disposed over the first etch stop layer, and an upper ELK dielectric layer disposed over the lower ELK dielectric layer;
• one or more metal layer structures disposed within the ELK dielectric layer;
• a first capping layer disposed over the ELK dielectric layer at positions between the one or more metal layer structures and having a density greater a density of the upper ELK dielectric layer;
• and
• a second capping layer disposed over the one or more metal layer structures.

A back-end-of-the-line (BEOL) layer of an integrated chip, comprising:

• a low-k dielectric layer disposed over a semiconductor substrate;
• a first capping layer comprising a first material located over the low-k dielectric layer;
• one or more metal layer structures disposed within the low-k dielectric layer and extending through the first capping layer so that the one or more metal layer structures are located between the first capping layer;
• and
• a second capping layer located over the one or more metal layer structures comprising a second material different than the first material, wherein the second capping layer has a greater thickness over the one or more metal layer structures than over the first capping layer.