US 2014/0209994 A1 · Embedded Cost-Efficient SONOS Non-Volatile Memory

Abstract

A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Claims20

Dependent claims

A CMOS integrated circuit (IC) comprising:

a semiconductor substrate:
a cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell including:
a source region and a drain region formed by dopant materials diffused into the substrate and spaced apart such that the source and drain regions are separated by a channel region,
a polycrystalline silicon (polysilicon) gate structure disposed over the channel region, and
an oxide-nitride-oxide (ONO) stack disposed between the substrate and the polysilicon gate structure and extending over the source and drain regions, said ONO stack including a nitride layer that is separated from the substrate by a first oxide layer and is separated from the polysilicon gate structure by a second oxide layer;
and
means disposed on the substrate for applying respective programming voltages to the source and drain regions and to the polysilicon gate structure such that channel hot electrons are generated in the channel region that become trapped in a portion of the nitride layer located over the channel region.

4 more elements

A CMOS circuit comprising an array of cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell groups, each said cell group comprising:

a shared drain region formed by a dopant material diffused into a semiconductor substrate;
four source regions formed by said dopant material diffused into the substrate adjacent to the shared drain region such that each of the four source regions is separated from a corresponding drain portion of said shared drain region by an associated channel region;
an oxide-nitride-oxide (ONO) stack layer disposed on the substrate over the channel regions defined between the shared drain region and the plurality of source regions, the ONO stack layer including a nitride layer sandwiched between an upper oxide layer and a lower oxide layer;
and
four gate structures disposed on the ONO stack such that each of the four gate structures is disposed over an associated said channel region.

2 more elements

A CMOS circuit disposed on a semiconductor substrate, the CMOS IC comprising:

an oxide-nitride-oxide (ONO) stack layer disposed on the substrate, the ONO stack layer including a nitride layer sandwiched between an upper oxide layer and a lower oxide layer;
a plurality of parallel polycrystalline silicon (polysilicon) word line structures disposed on the ONO stack layer;
a plurality of parallel bit line structures disposed over and extending perpendicular to the word line structures;
and
a plurality of cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cells arranged in rows and columns, wherein each of the plurality of CEONOS cells includes:
a source region and a drain region formed by dopant materials diffused into the substrate and spaced apart such that the source and drain regions are separated by a channel region,
a non-volatile storage element formed by an associated portion of said ONO stack layer that is disposed over the source, drain and channel regions of said each CEONOS NVM cell;
and
a gate structure formed by a portion of an associated word line structure of said plurality of word line structures disposed over said non-volatile storage element of said each CEONOS NVM cell,
wherein the source and drain regions of said each CEONOS NVM cell are respectively connected to associated first and second bit line structures by contact structures that extend from said substrate to said associated bit line structures through said ONO stack layer.

7 more elements

Dependencies are inferred from the claim text.

Embedded Cost-Efficient SONOS Non-Volatile Memory

Life of this patent

Embedded Cost-Efficient SONOS Non-Volatile Memory

Life of this patent

Abstract

Claims20