Non-Volatile Memory With Silicided Bit Line Contacts
AssigneeSpansion LLC
InventorsChing-Huang LU, Simon Siu-Sing CHAN, Hidehiko SHIRAIWA, Lei XUE
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Abstract
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
Claims22
A memory array having a plurality of charge trapping dielectric memory devices, comprising:
- a substrate having a first bit line and a second bit line formed therein and a body region interposed between the first and the second bit lines;
- a first dielectric layer disposed on the body region;
- a dielectric charge trapping layer disposed on the first dielectric layer;
- and
- a second dielectric layer disposed on the dielectric charge trapping layer, the first dielectric layer and the dielectric charge trapping layer extending beyond the second dielectric layer in a direction parallel to a top surface of the substrate.
A method comprising:
- disposing a first dielectric layer on a substrate;
- disposing a dielectric charge trapping layer on the first dielectric layer;
- disposing a second dielectric layer on the dielectric trapping layer;
- patterning a hard mask on the second dielectric layer;
- disposing an oxide spacer on sidewalls of the hard mask to leave exposed a bit line contact region;
- removing portions of the second dielectric layer, dielectric trapping layer and first dielectric layer beneath the bit line contact region;
- removing portions of the oxide space sidewalls to leave exposed a portion of the second dielectric layer;
- and
- removing the exposed portion of the second dielectric layer to thereby yield extended portions of the dielectric trapping layer and first dielectric layer.
A charge trapping dielectric memory device, comprising:
- a first dielectric layer disposed on a substrate;
- a dielectric charge trapping layer disposed on the first dielectric layer;
- and
- a second dielectric layer disposed on the dielectric charge trapping layer, the first dielectric layer and the dielectric charge trapping layer extending beyond the second dielectric layer in a direction parallel to a top surface of the substrate.
Dependencies are inferred from the claim text.