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US 2014/0209990 A1Published application
Semiconductor device and method of manufacturing thereof
AssigneeMacronix International Co., Ltd.
InventorChi-Pin Lu
Life of this patent
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Abstract
A memory device is provided having an improved gate coupling ratio, substantial suppression of p-type dopant segregation, and reduction in inter-poly dielectric current leakage. The memory device may be substantially free of any void spaces in a second conductive layer. Methods of manufacturing such a memory device are also provided.
Claims24
A semiconductor device comprising:
- a substrate;
- a first dielectric layer disposed on the substrate;
- a first conductive layer disposed on the first dielectric layer;
- a film that covers a bottom portion of the first conductive layer;
- a trench defined in the substrate;
- a liner layer substantially disposed along a sidewall of the trench;
- and
- a fill material disposed in the trench that substantially surrounds the film.
5 more elements
A semiconductor comprising:
- a first conductive layer having a top portion substantially rounded in shape;
- a film that covers a bottom portion of the first conductive layer;
- and
- a fill material that substantially surrounds the film.
1 more element
A method of fabricating a memory device comprising:
- providing a substrate, a first dielectric layer, and a first conductive layer;
- patterning the first dielectric layer and the first conductive layer;
- trimming a sidewall of the first conductive layer to form a film;
- forming a trench in the substrate;
- filling the trench with a fill material;
- rounding a top portion of the first conductive layer;
- forming a second dielectric layer on the first conductive layer;
- and
- forming a second conductive layer on the second dielectric layer.
6 more elements
Dependencies are inferred from the claim text.