Anti-fuse memory cell
AssigneeSidense Corp.
InventorWlodek KURJANOWICZ
Life of this patent
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Abstract
An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area.
Claims17
A method of forming a variable thickness gate oxide for an anti-fuse transistor, comprising the steps of:
- growing a first oxide in a channel region of the anti-fuse transistor;
- removing the first oxide from a thin oxide area of the channel region;
- thermally growing a second oxide in the thin oxide area and in a thick gate oxide area of the channel region under the first oxide, and a combination of the first oxide and the second oxide in the thick gate oxide area has a thickness greater than the second oxide in the thin oxide area;
- and
- forming a diffusion region adjacent the thick oxide area for receiving current from the channel region.
An anti-fuse memory cell having a variable thickness gate oxide comprising:
- a channel region in a substrate;
- a first oxide in a thick oxide area of the channel region;
- and,
- a second oxide in a thin oxide area of the channel region and in the thick oxide area underneath the first oxide;
- a diffusion region adjacent to the thick oxide area for receiving current from the channel region;
- isolation adjacent to the thin gate oxide area;
- and
- a gate over the first oxide and the second oxide.
Dependencies are inferred from the claim text.