Semiconductor Device With Multi Level Interconnects And Method Of Forming The Same

A semiconductor device comprising:

• a substrate including a gate structure traversing a channel region and separating source and drain (S/D) features, the gate structure including a gate electrode, the gate structure having a top surface in a first plane;
• a first dielectric layer formed over the S/D features;
• a first interconnect structure extending through the first dielectric layer and through an intermediate layer formed over the first dielectric layer, the first interconnect being in electrical contact with the S/D features, the first interconnect structure having a top surface in a second plane different from the first plane of the top surface of the gate structure;
• a second dielectric layer formed over the intermediate layer;
• a second interconnect structure extending through the second dielectric layer, the second interconnect being in electrical contact with the first interconnect structure;
• and
• a third interconnect structure extending through the second dielectric layer and through the intermediate layer, the third interconnect structure being in electrical contact with the gate structure.

A method of manufacturing comprising:

• providing a substrate including a gate structure separating source and drain (S/D) features;
• forming a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features;
• forming an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure;
• and
• forming a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.