Semiconductor Device Including an Edge Area and Method of Manufacturing a Semiconductor Device

A power field effect transistor, comprising a semiconductor portion, the semiconductor portion comprising:

• a semiconductor layer including a drift zone of a first conductivity type and at least one impurity zone of a second, opposite conductivity type that directly adjoins a first surface of the semiconductor portion in an element area;
• a connection layer of the first conductivity type directly adjoining the semiconductor layer opposite to the first surface, wherein a mean impurity concentration in the connection layer is at least ten times greater than a mean impurity concentration in the drift zone;
• and
• an overcompensation zone of the second conductivity type in an edge area, the edge area surrounding the element area and directly adjoining an outer surface tilted to the first surface, wherein, in a projection of the overcompensation zone vertical to the first surface, a portion of the drift zone is arranged between the first surface and the overcompensation zone.

A power insulated gate bipolar transistor, comprising a semiconductor portion, the semiconductor portion comprising:

• a semiconductor layer including a drift zone of a first conductivity type and at least one impurity zone of a second, opposite conductivity type that directly adjoins a first surface of the semiconductor portion in an element area;
• a connection layer of the second conductivity type directly adjoining the semiconductor layer opposite to the first surface, wherein a mean impurity concentration in the connection layer is at least ten times greater than a mean impurity concentration in the drift zone;
• and
• an overcompensation zone of the first conductivity type in the semiconductor portion in an edge area, the edge area surrounding the element area and directly adjoining an outer surface titled to the first surface, wherein, in a projection of the overcompensation zone vertical to the first surface, a portion of the drift zone is arranged between the first surface and the overcompensation zone.

A method of manufacturing a semiconductor device, the method comprising:

• providing a semiconductor layer comprising a drift zone of a first conductivity type, the semiconductor layer adjoining a connection layer, wherein a mean impurity concentration in the connection layer is at least ten times a mean impurity concentration in the drift zone;
• providing an overcompensation zone of a conductivity type opposite to the conductivity type of the connection layer in an edge area, the edge area surrounding an element area and directly adjoining an outer surface titled to the first surface, wherein in a projection of the overcompensation zone vertical to an interface between the connection layer and the semiconductor layer a portion of the drift zone is arranged between the first surface and the overcompensation zone;
• and
• providing, in the element area, at least one impurity zone of a second conductivity type, which is complementary to the first conductivity type, the at least one impurity zone adjoining a first surface of the semiconductor layer opposite to the connection layer.