Pixel unit and pixel array

A pixel array, adapted to a display panel, the pixel array comprising:

• a plurality of first gate lines;
• a plurality of second gate lines, wherein the first gate lines and the second gate lines are alternately arranged in sequence;
• a data line, intersecting the first gate lines and the second gate lines;
• and
• a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, arranged and constituting a plurality of row sub-pixels, each of the row sub-pixels comprising a first sub-pixel, a second sub-pixel and a third sub-pixel, wherein
• each of the first sub-pixels comprises a first pixel electrode and a first active switching device, wherein the first active switching device comprises a first gate electrode, a first source electrode and a first drain electrode, the first gate electrode is electrically connected to the corresponding second gate line, and the first drain electrode is electrically connected to the first pixel electrode,
• each of the second sub-pixels comprises a second pixel electrode and a second active switching device, wherein the second active switching device comprises a second gate electrode, a second source electrode and a second drain electrode, the second gate electrode is electrically connected to the corresponding second gate line, the second source electrode is electrically connected to the data line, and the second drain electrode is electrically connected to the second pixel electrode,
• each of the third sub-pixels comprises a third pixel electrode and a third active switching device, wherein the third active switching device comprises a third gate electrode, a third source electrode and a third drain electrode, the third gate electrode is electrically connected to the corresponding first gate line, the third source electrode is electrically connected to the data line, and the third drain electrode is electrically connected to the third pixel electrode and the first source electrode corresponding to the third drain electrode,
• wherein
• the first gate electrode of the first sub-pixel located in an (n+1)-th row of the row sub-pixels is electrically connected to an m-th of the second gate lines,
• the second gate electrode of the second sub-pixel located in the (n+1)-th row of the row sub-pixels is electrically connected to the m-th of the second gate lines,
• the third gate electrode of the third sub-pixel located in an n-th row of the row sub-pixels is electrically connected to an m-th of the first gate lines, and the third drain electrode of the third sub-pixel located in the n-th row of the row sub-pixels is electrically connected to the first source electrode of the first sub-pixel located in the (n+1)-th row of the row sub-pixels, and
• the third gate electrode of the third sub-pixel located in the (n+1)-th row of the row sub-pixels is electrically connected to an (m+1)-th of the first gate lines.