Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

A method, comprising:

• providing a semiconductor substrate;
• depositing an isolation layer on the semiconductor substrate;
• depositing a channel layer on the isolation layer, the channel layer to provide a channel for a transistor;
• and
• forming a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, material of the channel layer and to provide a source terminal or drain terminal for the transistor.

A system, comprising:

• a processor;
• and
• a memory device coupled with the processor, the processor or the memory device including:
• a semiconductor substrate;
• an isolation layer formed on the semiconductor substrate;
• a channel layer including nanowire material formed on the isolation layer, the channel layer to provide a channel for a transistor;
• and
• a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.