Nanowire Capacitor for Bidirectional Operation

An electronic device, comprising:

• at least one first set of nanowires and first set pads etched in an SOI layer of an SOI wafer and at least one second set of nanowires and second set of pads etched in the SOI layer, wherein the first set of pads are attached at opposite ends of the first set of nanowires in a ladder-like configuration and wherein the second set of pads are attached at opposite ends of the second set of nanowires in a ladder-like configuration;
• a first gate stack that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device, wherein portions of the first set of nanowires extending out from the gate stack and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are undoped;
• a second gate stack that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device, wherein portions of the second set of nanowires extending out from the gate stack and the second set of pads serve as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped;
• a first silicide formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack;
• and
• a second silicide formed on the source and drain regions of the FET device.